A novel digital chirp generator using a dual clock field programmable gate array architecture

The use of digital frequency synthesizers (FSs) to generate chirp signals is discussed. Digital generation methods include: (a) waveform synthesis by memory devices/digital processing devices, and (b) direct digital frequency synthesis (DDFS). The DDFS is usually programmed by either a counter or a frequency accumulator (FA). The digitally generated chirp signal has a stepped frequency vs time characteristic which results in unwanted sidebands. Their level can be kept below the noise level of the synthesizer by a proper choice of the frequency step size and its update rate. However, due to the digital nature of the DDFS, the tendency has become to use synthesizers with very fine frequency resolution and a frequency update rate equal to the operating speed of the synthesizer. To cover the HF frequency band, this requires the use of either ECL logic or GaAs logic which consume more power than conventional TTL or fast CMOS and are more difficult to construct. In addition, FSs with very fine frequency resolution require a large size FA. Expressions for the sideband levels of the generated/demodulated signals are given. The increased complexity of the programmer does not result in improved performance. A new architecture which uses a double accumulator and a dual clock is proposed. This enables the use of TTL or CMOS logic for the FA which reduces the power consumption/noise. Also, the duration of the sweep signal can be controlled independently of the output frequency. A prototype dual clock chirp generator using on gate arrays is presented.