Detection System-on-Chip

Bioluminescence whereby light is emitted as a result of a chemical reaction offers several advantages over other assay methods, such as fluorescence, including low background and the utilization of reagents with extended shelf life [1]. Also, since no filters or excitation sources are needed, lab-on-chip integration is considerably easier. Of special interest are luciferase-based assay methods with a 560nm emission peak that are used to detect pathogens and proteins, perform gene expression and regulation studies, and sequence DNA. Today's commercial luminescence detection systems use expensive, cooled CCD-based camera setups and require many microliter volumes of costly reagents due to the high loss in their optical paths. There is growing need for miniaturized low cost luminescence detection systems for environmental and biomedical diagnostics. To address this need systems in which the luminescent chemistry is directly coupled to the detector surface, and therefore must be operated at room temperature [2] are being investigated. This work is targeted to a set of applications, including nucleic acid, protein and pathogen detection, which require 1-1000 assay sites each of size 150x150µm 2 and have reaction times of 1-30s with a minimum emission rate of 4x10 5 photons/cm 2 .s (10-6 lux). As off-the-shelf CCD and CMOS imagers cannot satisfy these requirements, a detection chip having a pixel array with the same pitch as the assay site array is designed and fabricated. A block diagram of the chip, which is fabricated in a 0.18µm CMOS process [3], is given in Fig. 12.3.1. It comprises three main sections, an 8x16 pixel array, a per-pixel 13b 2-step ADC, and a column-level DSP SIMD array. To achieve low read noise, a pseudo-differential pixel and ADC architecture is used. The pixel comprises a P+/N/Psub photodiode, an NMOS reset gate and two PMOS source followers one connected to the photodiode and the other connected to a global reference signal VREF. A PMOS follower circuit is used to lower photodiode operating voltage range to reduce dark current and to achieve high linearity. Each pixel's pseudo-differential output is connected to a separate ADC channel consisting of a VGA, a 1b differential comparator and a 4b DAC as shown in Fig. 12.3.2. A per-pixel ADC design is chosen to (i) achieve over seven 13b MS/s using simple low frequency circuits, (ii) reduce noise bandwidth, (iii) provide architecture scalability, and (iv) eliminate switching noise. The VGA employs a fully differential amplifier with a non-sili-cided P+ …