The Pseudorandom Test Pattern Generation Oriented to Power Dissipation

As the increase of Integrated Circuits′ design complexity and process complexity, the Integrated Circuits′ test are faced with more and more challenges. Built in self test, as a new method of design for testability, can prominently improve the testability of random logic in the circuits, resolve a series of test problem, but bring the power dissipation problem during test mode. In this paper a new test pattern generation method is proposed, which can greatly reduce the power dissipation during test mode and has no impact on the fault coverage.