Optimum VDD for Minimum Energy

Operating circuits in the sub-threshold region or near the sub-threshold design can yield extremely low power circuits. However, for most applications that require ultra-low power, the lowest power solution is not necessarily the optimal solution from a minimum energy point of view. In this chapter, we describe a technique to find the energy optimum VDD value for a design, and show that for minimum energy consumption, the circuit may need to be operated at VDD values that are slightly higher than the NMOS threshold voltage value. We study this problem in the context of designing a circuit using a network of dynamic NOR-NOR PLAs.

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