A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Nanoscale resistive memory devices are expected to fuel dense integration of electronic synapses for large-scale neuromorphic systems. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in situ learning and computing while driving a large number of resistive synapses is desired. This brief presents a novel leaky integrate-and-fire neuron design that implements the dual-mode operation of current integration and synaptic drive, with a single operational amplifier (opamp) and enables in situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18-μm CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses and demonstrate in situ associative learning. The neuron circuit occupies a small area of 0.01 mm2 and has an energy efficiency value of 9.3 pJ/spike/synapse.

[1]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[2]  Pinaki Mazumder,et al.  CMOS and Memristor-Based Neural Network Design for Position Detection , 2012, Proceedings of the IEEE.

[3]  Fabien Alibart,et al.  Plasticity in memristive devices for spiking neural networks , 2015, Front. Neurosci..

[4]  Yuchao Yang,et al.  Building Neuromorphic Circuits with Memristive Devices , 2013, IEEE Circuits and Systems Magazine.

[5]  Mostafa Rahimi Azghadi,et al.  Spike-Based Synaptic Plasticity in Silicon: Design, Implementation, Application, and Challenges , 2014, Proceedings of the IEEE.

[6]  Marc'Aurelio Ranzato,et al.  Building high-level features using large scale unsupervised learning , 2011, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

[7]  André van Schaik,et al.  A generalised conductance-based silicon neuron for large-scale spiking neural networks , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[8]  Luping Shi,et al.  Enabling an Integrated Rate-temporal Learning Scheme on Memristor , 2014, Scientific Reports.

[9]  Julie Grollier,et al.  Silicon neuron dedicated to memristive spiking neural networks , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[10]  Antoine Joubert,et al.  A robust and compact 65 nm LIF analog neuron for computational purposes , 2011, 2011 IEEE 9th International New Circuits and systems conference.

[11]  T. Serrano-Gotarredona,et al.  Design of adaptive nano/CMOS neural architectures , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[12]  W. Marsden.  I and J , 2012 .

[13]  Narayan Srinivasa,et al.  Energy-Efficient Neuron, Synapse and STDP Integrated Circuits , 2012, IEEE Transactions on Biomedical Circuits and Systems.

[14]  Sylvain Saïghi,et al.  Excitatory and Inhibitory Memristive Synapses for Spiking Neural Networks , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[15]  Gregory S. Snider,et al.  Spike-timing-dependent learning in memristive nanodevices , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[16]  Gert Cauwenberghs,et al.  Neuromorphic Silicon Neuron Circuits , 2011, Front. Neurosci.