An all-digital architecture for low-jitter regulated delay lines

A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suffers from the presence of a limit cycle that produces periodic jitter. A tight trade-off exists between jitter and DAC resolution. This paper proposes an all-digital architecture of regulated delay line based on a digital first-order ΔΣ modulator and a single-bit DAC, which eliminates the need for the high-resolution DAC and trades jitter against bandwidth. A theoretical estimation of the jitter induced by the ΔΣ quantization noise is provided. The realized delay-locked loop generates 16 phases of the 3–4 GHz input signal in a 90-nm CMOS technology. The simulated delay jitter of 30 fs rms confirms the theoretical estimation.

[1]  Liu Shen-Iuan,et al.  A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $\mu{\hbox {m}}$ CMOS Technology , 2007, IEEE Journal of Solid-State Circuits.

[2]  Nicola Da Dalt,et al.  Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Yiu-Fai Chan,et al.  A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[4]  Yorgos Palaskas,et al.  A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Salvatore Levantino,et al.  Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Nicola Da Dalt.  A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Young-Hyun Jun,et al.  A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces , 2009, IEEE Journal of Solid-State Circuits.

[8]  Rong-Jyi Yang,et al.  A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology , 2007, IEEE J. Solid State Circuits.

[9]  S.L.J. Gierkink,et al.  Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump , 2008, IEEE Journal of Solid-State Circuits.

[10]  Enrico Temporiti,et al.  A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques , 2009, IEEE Journal of Solid-State Circuits.