Analytical Evaluation of Energy and Throughput for Multilevel Caches

With the increase of processor-memory performance gap, it has become important to gauge the performance of cache architectures so as to evaluate their impact on energy requirement and throughput of the system. Multilevel caches are found to be increasingly prevalent in the high-end processors. Additionally, the recent drive towards multicore systems has necessitated the use of multilevel cache hierarchies for shared memory architectures. This paper presents simplified and accurate mathematical models to estimate the energy consumption and the impact on throughput for multilevel caches for single core systems.

[1]  Klaus D. McDonald-Maier,et al.  Towards Increased Power Efficiency in Low End Embedded Processors: Can Cache Help? , 2008 .

[2]  Leonard J. Shustek,et al.  An instruction timing model of CPU performance , 1977, ISCA '77.

[3]  Tarek M. Taha,et al.  An Instruction Throughput Model of Superscalar Processors , 2008, IEEE Trans. Computers.

[4]  Kanad Ghose,et al.  Analytical energy dissipation models for low-power caches , 1997, ISLPED '97.

[5]  K. Ghose,et al.  Modeling Energy Dissipation in Low Power Caches , 1998 .

[6]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[7]  T. Wada,et al.  An analytical access time model for on-chip cache memories , 1992 .

[8]  Mike Tien-Chien Lee,et al.  Power analysis of a 32-bit embedded microcontroller , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[9]  Sang Lyul Min,et al.  An Accurate Worst Case Timing Analysis for RISC Processors , 1995, IEEE Trans. Software Eng..

[10]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[12]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[13]  Luca Benini,et al.  Cycle-accurate simulation of energy consumption in embedded systems , 1999, DAC '99.

[14]  Klaus D. McDonald-Maier,et al.  Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors , 2009, EURASIP J. Embed. Syst..

[15]  Jörg Henkel,et al.  A framework for estimation and minimizing energy dissipation of embedded HW/SW systems , 1998, DAC.

[16]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[17]  Manuel E. Acacio,et al.  Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures , 2007, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07).

[18]  Christopher J. Hughes,et al.  RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors , 2002, Computer.

[19]  Pinar Korkmaz,et al.  ENERGY MODELING OF A PROCESSOR CORE USING SYNOPSYS AND OF MEMORY HIERARCHY USING KAMBLE AND GHOSE MODEL , 2002 .

[20]  Muhammad Yasir Qadri.  Cache-Energy and Throughput Models : A Design Exploration for Overhead Analysis , 2008 .