Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V.

[1]  H. Fu,et al.  A high-speed bipolar technology featuring self-aligned single-poly base and submicrometer emitter contacts , 1990, IEEE Electron Device Letters.

[2]  Koichiro Mashiko,et al.  A voltage compensated series-gate bipolar circuit operating at sub-2 V , 1993 .

[3]  Z. H. Lao,et al.  A 20-Gb/s silicon bipolar 1:4-demultiplexer IC , 1994 .

[4]  D. Clawin,et al.  Silicon bipolar 14 Gb/s 1:4-demultiplexer IC regarding system requirements , 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[5]  P. Weger,et al.  2V low-power bipolar logic , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[6]  C. Stout,et al.  10 Gb/s Silicon Bipolar 8:1 Multiplexer And 1:8 Demultiplexer , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.