A built-in self-test and self-diagnosis scheme for embedded SRAM

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.

[1]  Paolo Prinetto,et al.  Industrial BIST of embedded RAMs , 1995, IEEE Design & Test of Computers.

[2]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[3]  V. K. Agarwal,et al.  Built-in self-diagnosis for repairable embedded RAMs , 1993, IEEE Design & Test of Computers.

[4]  A.J. van de Goor,et al.  RAM diagnostic tests , 1996, IEEE International Workshop on Memory Technology, Design and Testing,.

[5]  Cheng-Wen Wu,et al.  RAMSES: a fast memory fault simulator , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[6]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Elizabeth M. Rudnick,et al.  Diagnostic testing of embedded memories using BIST , 2000, DATE '00.

[8]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..

[9]  Bruce F. Cockburn.  Tutorial on semiconductor memory testing , 1994, J. Electron. Test..

[10]  Cheng-Wen Wu.  Testing Embedded Memories: Is BIST The Ultimate Solution? , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[11]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[12]  Cheng-Wen Wu,et al.  Simulation-based test algorithm generation for random access memories , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[13]  Cheng-Wen Wu,et al.  Error catch and analysis for semiconductor memories using March tests , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[14]  Bruce F. Cockburn,et al.  An optimal march test for locating faults in DRAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[15]  Frans P. M. Beenker,et al.  Fault modeling and test algorithm development for static random access memories , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.