Method for manufacturing layers required by integrated circuit layout registration

The invention discloses a method for manufacturing layers required by integrated circuit layout registration. The method includes the following steps that a data file of the gds format of an integrated circuit layout is introduced into planishing; a certain layer with process features is selected, and the layer is printed to form an electronic document file; the page margins of pages of picture files are set sequentially, graphs unrelated to the layout graphs are removed, only the layout graphs are reserved, and the adjacent layout graphs to be spliced are made to be right aligned with the page margins and are converted into a plurality of files of the jpeg format of the layer; the files of the jpeg format of the layer are selected, shapes of chip layouts are compared, the corresponding positions of the files of the jpeg format are set and are spliced into a graphic file; the spliced graphic file is evaluated; the manufactured files of all the layers are gathered to one file, and the layer files for the integrated circuit layout registration are formed. By means of the method, the splicing workload is lowered, the splicing accuracy is improved, and the requirement for layer manufacturing is met.