B.S.T.J. brief: Serial coding for cyclic block codes

In 1972 the concept of seriol encoding and decoding for single, error correcting BCH codes was introduced.1,2 In this note, the concept of serial encoding and decoding is generolized and the timing diagrams are presented for a typical (n, k) cyclic block code. The implementation in conventional tecnology uses only one exclusive-OR gate and is presented for all (n - k) order generator polynomials for any code n bits long. The implementations presented are valid for all eyclic block encoders and for all decoders with single error correction with multiple error detection capability.