A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar
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[1] Scott Hauck,et al. The Roles of FPGA's in Reprogrammable Systems , 1998 .
[2] D. Strukov,et al. CMOL: Devices, Circuits, and Architectures , 2006 .
[3] J. F. Stoddart,et al. Nanoscale molecular-switch crossbar circuits , 2003 .
[4] Kaushik Roy,et al. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Hiromichi Kataura,et al. Logic circuits using solution-processed single-walled carbon nanotube transistors , 2008 .
[6] Shashi Shekhar,et al. Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[7] Swarup Bhunia,et al. Reconfigurable computing using content addressable memory for improved performance and resource usage , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[8] Dmitri B. Strukov,et al. Prospects for the development of digital CMOL circuits , 2007, 2007 IEEE International Symposium on Nanoscale Architectures.
[9] A. Toriumi,et al. Programmable single-electron transistor logic for low-power intelligent Si LSI , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[10] Fabrizio Lombardi,et al. Design of a QCA memory with parallel read/serial write , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).
[11] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[12] Seth Copen Goldstein,et al. NanoFabrics: spatial computing using molecular electronics , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.
[13] R. Service,et al. Molecules Get Wired , 2001, Science.
[14] Mircea R. Stan,et al. CMOS/nano co-design for crossbar-based molecular electronic systems , 2003 .
[15] R. D. Blanton,et al. CAEN-BIST: testing the nanofabric , 2004, 2004 International Conferce on Test.
[16] Scott Hauck,et al. The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.
[17] André DeHon,et al. Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[18] Stoddart,et al. Electronically configurable molecular-based logic gates , 1999, Science.
[19] Bonnie A. Sheriff,et al. A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre , 2007, Nature.
[20] K. Roy,et al. Performance estimation of molecular crossbar architecture considering capacitive and inductive coupling between interconnects , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
[21] P. Lugli,et al. Read-Out Design Rules for Molecular Crossbar Architectures , 2009, IEEE Transactions on Nanotechnology.
[22] C. Dekker,et al. Logic Circuits with Carbon Nanotube Transistors , 2001, Science.
[23] Seth Copen Goldstein,et al. Molecular electronics: from devices and interconnect to circuits and architecture , 2003, Proc. IEEE.
[24] D. Ohlberg,et al. One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography , 2005 .
[25] Mehdi Baradaran Tahoori,et al. A mapping algorithm for defect-tolerance of reconfigurable nano-architectures , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[26] Mircea R. Stan,et al. Design and analysis of crossbar circuits for molecular nanoelectronics , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.
[27] Mircea R. Stan,et al. A universal device model for nanoelectronic circuit simulation , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.
[28] Gustavo de Veciana,et al. Scalable defect mapping and configuration of memory-based nanofabrics , 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..
[29] D. Jones,et al. A time-multiplexed FPGA architecture for logic emulation , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[30] Mark Mohammad Tehranipoor,et al. A new hybrid FPGA with nanoscale clusters and CMOS routing , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[31] R. Williams,et al. Nano/CMOS architectures using a field-programmable nanowire interconnect , 2007 .
[32] S.C. Goldstein,et al. Digital logic using molecular electronics , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[33] Narayanan Vijaykrishnan,et al. Exploring technology alternatives for nano-scale FPGA interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..