Partitioning mechanism based on dynamic Allocation of Data entries for chip multiprocessors

Exploiting the locality of blocks in the same set, LRU replacement strategy has deficiencies to manage L2 cache resources as the temporal locality has filtered by L1 caches. Instead, reuse replacement strategy [1] develops the reuse characteristics of blocks in entire cache scope being more potential to improve cache resources utilization. We use reuse replacement to manage L2 cache resources in chip multiprocessors (CMP) and propose a new partitioning mechanism named PAD (Partitioning based on dynamic Allocation of Data entries). PAD divides the tag array into sub-arrays and the data array into private and shared data regions, and partitions cache resources among cores depending on their memory access demand. As data entries are dynamically allocated to tag entries by reuse replacement strategy, a core that have obtained more data entries in time interval can have a higher demand of cache resources. Collecting occupied data entries, a PAD algorithm with initial, partitioning and rollback stages is proposed to decide the amount of cache resources assigned to each core. Capacity adjustment is accomplished by allocating data entries from the private data region or the shared data region. Using programs from PARSEC benchmark to build multi-threaded and multi-programmed applications, our experiments show that this new scheme can achieve an average IPC improvement of 22.33% on both traditional private and shared cache organizations.