Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications

Abstract Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ -Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f T , in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.

[1]  S. Inoue,et al.  Dependence of single-crystalline Si TFT characteristics on the channel position inside a location-controlled grain , 2005, IEEE Transactions on Electron Devices.

[2]  J. Seto.  The electrical properties of polycrystalline silicon films , 1975 .

[3]  C.I.M. Beenakker,et al.  Single-grain Si thin-film transistors for analog and RF circuit applications , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[4]  E. Menard,et al.  High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates , 2006, IEEE Electron Device Letters.

[5]  Tatsuya Shimoda,et al.  High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process( Electronic Displays) , 2004 .

[6]  P. J. Scanlon,et al.  Conductivity behavior in polycrystalline semiconductor thin film transistors , 1982 .

[7]  S. Adriaensen,et al.  A voltage reference compatible with standard SOI CMOS processes and consuming 1 pA to 50 nA from room temperature up to 300/spl deg/C , 2002, 2002 IEEE International SOI Conference.

[8]  J. W. Metselaar,et al.  Microstructure characterization of location-controlled Si-islands crystallized by excimer laser in the μ-Czochralski (grain filter) process , 2007 .

[9]  O. Rozeau,et al.  Polysilicon high frequency devices for large area electronics: Characterization, simulation and modeling , 2007 .

[10]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[11]  J. W. Metselaar,et al.  Electrical property of coincidence site lattice grain boundary in location-controlled Si island by excimer-laser crystallization , 2005 .

[12]  Ryoichi Ishihara,et al.  Formation of location-controlled crystalline islands using substrate-embedded seeds in excimer-laser crystallization of silicon films , 2001 .

[13]  Trond Ytterdal,et al.  SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors , 1997 .