Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

We present a scheme to optimize power consumption in data-path scheduling and binding with resources operating at multiple supply voltages and threshold voltages by simulated annealing. The proposed scheme considers both scheduling and binding simultaneously such that we have a wider solution space to explore and a solution with much lower power can be obtained. Besides, we give a more accurate high-level power model so that not only the dynamic and leakage power of function units but also the sharing of function units is taken into account. Experimental results on a number of high-level benchmark circuits using three supply voltage and threshold voltage levels show that an average power saving of about 68% can be obtained compared to using a single supply and threshold voltage level (with a time constraint of 1.2 times the critical path delay and a resource constraint of two function units of each type).

[1]  Radu Marculescu,et al.  Improving the efficiency of power simulators by input vector compaction , 1996, DAC '96.

[2]  A. Chatterjee,et al.  Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[3]  A. Kumar,et al.  Minimizing switchings of the function units through binding for low power , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[4]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[5]  Jui-Ming Chang,et al.  Energy Minimization Using Multiple Supply Voltages , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Majid Sarrafzadeh,et al.  Accurate high level datapath power estimation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[7]  Henry Selvaraj,et al.  A scheduling and partitioning scheme for low power circuit operating at multiple voltages , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[8]  Srinivas Katkoori,et al.  Resource allocation and binding approach for low leakage power , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[9]  Dennis Sylvester,et al.  Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  C. Chakrabarti,et al.  A low power scheduling scheme with resources operating at multiple voltages , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Niraj K. Jha,et al.  Leakage power analysis and reduction during behavioral synthesis , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Dennis Sylvester,et al.  Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..