VLSI algorithms, architectures, and implementation of a versatile GF(2/sup m/) processor

This paper presents an extensive model and algorithms for detecting faults in SRAM-based dual-port and uni-port CAMs (Content Addressable Memories). This model is based on analyzing the functionalities of a cell of an SRAM-based CAM and dividing it into two parts (storage and comparison parts). It is shown that faults can affect one or both parts. While storage faults can be detected using a traditional test algorithm (such as the March C), faults affecting the comparison part of the cell require a substantially different approach. A complete characterization of these faults is presented; by analyzing the structure of the cell in the dual and uni-port configurations, physical faults (such as stuck-at, stuck-open, stuck-on, bridge) in lines and transistors can be mapped to three functional fault sets by the execution of the comparison operation. Two new detection algorithms (directly compatible with the world-oriented March C algorithm, as widely used in existing commercial tools) are proposed; 100 percent coverage is achieved. The first algorithm (Concurrent Detection Algorithm or CDA) employs concurrent operations for testing a dual-port CAM; the second algorithm (Non Concurrent Detection Algorithm or NCDA) uses nonconcurrent operations and can be used for testing dual-port as well as uni-port CAMs. CDA requires eight passes and (10N+2L) tests, where N is the number of words of the CAM and L is the width of a word. NCDA requires eight passes, too, but (12N+2L) tests. The number of tests required by CDA (and NCDA, too) is significantly less than required by existing algorithms.

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