Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures
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Paolo Bernardi | Davide Appello | Giorgio Pollaccia | Vincenzo Tancorre | A. Calabrese | S. Littardi | S. Quer | R. Ugioli | S. Quer | D. Appello | V. Tancorre | P. Bernardi | G. Pollaccia | S. Littardi | R. Ugioli | A. Calabrese
[1] Paolo Bernardi,et al. A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[2] Wu-Tung Cheng,et al. A Robust Automated Scan Pattern Mismatch Debugger , 2008, 2008 17th Asian Test Symposium.
[3] Witold A. Pleskacz,et al. AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).
[4] 上村 恭平,et al. Hardware Description Languageにおけるコードクローンのパターン分類 , 2015 .
[5] Paolo Bernardi,et al. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers , 2008, 2008 Design, Automation and Test in Europe.