Reducing power dissipation during test using scan chain disable

A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the circuit. Moreover, disabling the clock also reduces power dissipation in the clock tree which often is a major source of power. The only hardware modification that is required to implement this approach is to add the capability for the tester to gate the clock for one subset of the scan chains in the core. A procedure for generating and ordering the test set to maximize the we of scan disable is described. Experimental results are shown indicating that the proposed approach can significantly reduce both logic and clock power during testing.

[1]  R. Gupta,et al.  Configuring multiple scan chains for minimum test time , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[2]  Chen-Shang Lin,et al.  Test time reduction in scan designed circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[3]  Nur A. Touba,et al.  Static compaction techniques to control scan vector power dissipation , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[4]  Melvin A. Breuer,et al.  Configuring multiple scan chains for minimum test time , 1992, ICCAD.

[5]  Jhing-Fa Wang,et al.  Overall consideration of scan design and test generation , 1992, ICCAD.

[6]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 2000, J. Electron. Test..

[7]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[8]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  Alfred L. Crouch,et al.  Design-For-Test For Digital IC's and Embedded Core Systems , 1999 .

[10]  Kozo Kinoshita,et al.  Reduced scan shift: a new testing method for sequential circuits , 1994, Proceedings., International Test Conference.

[11]  Sandeep K. Gupta,et al.  ATPG for heat dissipation minimization during scan testing , 1997, DAC.

[12]  Sandeep K. Gupta,et al.  LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Sandeep K. Gupta,et al.  ATPG for heat dissipation minimization during test application , 1994, Proceedings., International Test Conference.

[14]  Jhing-Fa Wang,et al.  Overall consideration of scan design and test generation , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[15]  Sandeep K. Gupta,et al.  DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.

[16]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Alfred L. Crouch,et al.  Optimization trade-offs for vector volume and test power , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[18]  Patrick Girard,et al.  A test vector inhibiting technique for low energy BIST design , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[19]  Melvin A. Breuer,et al.  Ordering storage elements in a single scan chain , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[20]  Patrick Girard,et al.  Low power BIST design by hypergraph partitioning: methodology and architectures , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[21]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[22]  Sandeep K. Gupta,et al.  ATPG for Heat Dissipation Minimization During Test Application , 1998, IEEE Trans. Computers.

[23]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[24]  Chauchin Su,et al.  A serial scan test vector compression methodology , 1993, Proceedings of IEEE International Test Conference - (ITC).

[25]  Vishwani D. Agrawal,et al.  Power constraint scheduling of tests , 1994, Proceedings of 7th International Conference on VLSI Design.

[26]  Olivier Coudert,et al.  On solving covering problems , 1996, DAC '96.