Automatic test generation of linear analog circuits under parameter variations
暂无分享,去创建一个
[1] Abhijit Chatterjee,et al. Fault-based automatic test generator for linear analog circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[2] M. Soma. Automatic test generation algorithms for analogue circuits , 1996 .
[3] Mani Soma,et al. Analytical fault modeling and static test generation for analog ICs , 1994, ICCAD.
[4] R. Dandapani,et al. Test generation for linear analog circuits , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[5] C.-J. Richard Shi,et al. Rapid frequency-domain analog fault simulation under parameter tolerances , 1997, DAC.
[6] Abhijit Chatterjee,et al. Fault-based automatic test generator for linear analog circuits , 1993, ICCAD.
[7] Alberto L. Sangiovanni-Vincentelli,et al. Testing of analog systems using behavioral models and optimal experimental design techniques , 1994, ICCAD.
[8] Sheng-Jen Tsai,et al. Test Vector Generation for Linear Analog Devices , 1991, 1991, Proceedings. International Test Conference.
[9] E. Felt,et al. Testing Of Analog Systems Using Behavioral Models And Optimal Experimental Design Techniques , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[10] C.-J. Richard Shi,et al. Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis , 1999, TODE.
[11] Alberto L. Sangiovanni-Vincentelli,et al. Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Olivier Coudert,et al. Two-level logic minimization: an overview , 1994, Integr..
[13] C.-J.R. Shi,et al. Efficient DC fault simulation of nonlinear analog circuits , 1998, Proceedings Design, Automation and Test in Europe.
[14] Pierre Duhamel,et al. Automatic test generation techniques for analog circuits and systems: A review , 1979 .
[15] C.-J. Richard Shi. Block-level fault isolation using partition theory and logic minimization techniques , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.
[16] A. Householder. A Survey of Some Closed Methods for Inverting Matrices , 1957 .
[17] Wojciech Maly,et al. VLSI Design for Manufacturing: Yield Enhancement , 1989 .
[18] Georges G. E. Gielen,et al. Automated test pattern generation for analog integrated circuits , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[19] Mani Soma,et al. Analytical Fault Modeling And Static Test Generation For Analog ICs , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[20] Kwang-Ting Cheng,et al. Test generation for linear time-invariant analog circuits , 1999 .
[21] Bozena Kaminska,et al. LIMSoft: automated tool for design and test integration of analog circuits , 1996, Proceedings International Test Conference 1996. Test and Design Validity.