Implementation of CPA analysis against AES design on FPGA

Physical implementations of cryptographic algorithms may let relatively side channel information. By analyzing this information leakage, the confidential data, like the cryptographic keys, can be revealed. The correlation power analysis(CPA) is a well-known attack of the cryptographic device. This paper conduces a successful CPA of the Advanced Encryption Standard AES implemented on the Xilinx FPGA with the Side-channel Attack Standard Evaluation Board (SASEBO). The experimental results show that the choice of the power model and the number of power traces can further improve the performance of CPA attack in extracting the correct key.

[1]  Rita Mayer-Sommer,et al.  Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards , 2000, CHES.

[2]  Denis Flandre,et al.  Dynamic differential self-timed logic families for robust and low-power security ICs , 2007, Integr..

[3]  Ingrid Verbauwhede,et al.  Partition vs. Comparison Side-Channel Distinguishers , 2008 .

[4]  Jean-Louis Lacoume,et al.  A Proposition for Correlation Power Analysis Enhancement , 2006, CHES.

[5]  Rached Tourki,et al.  Optimized power trace numbers in CPA attacks , 2011, Eighth International Multi-Conference on Systems, Signals & Devices.

[6]  Jean-Sébastien Coron,et al.  Statistics and secret leakage , 2000, TECS.

[7]  Emmanuel Prouff,et al.  Theoretical and practical aspects of mutual information-based side channel analysis , 2010, Int. J. Appl. Cryptogr..

[8]  Simon W. Moore,et al.  Security evaluation against electromagnetic analysis at design time , 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

[9]  Takeshi Sugawara,et al.  Enhanced Correlation Power Analysis Using Key Screening Technique , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[10]  Yongdae Kim,et al.  Biasing power traces to improve correlation in power analysis attacks , 2010 .

[11]  Christophe Clavier,et al.  Differential Power Analysis in the Presence of Hardware Countermeasures , 2000, CHES.

[12]  Wieland Fischer,et al.  Differential Power Analysis of Stream Ciphers , 2007, CT-RSA.

[13]  FRANÇOIS-XAVIER STANDAERT,et al.  An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays , 2006, Proceedings of the IEEE.

[14]  Christophe Clavier,et al.  Correlation Power Analysis with a Leakage Model , 2004, CHES.

[15]  Ingrid Verbauwhede,et al.  Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices , 2009, ICISC.

[16]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.