Trigate nanowire MOSFETs analog figures of merit

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225°C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed.

[1]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[2]  O. Faynot,et al.  Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width , 2013, IEEE Transactions on Electron Devices.

[3]  O. Faynot,et al.  High-temperature perspectives of UTB SOI MOSFETs , 2011, Ulis 2011 Ultimate Integration on Silicon.

[4]  Stephane Monfray,et al.  Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width , 2013 .

[5]  Willy Sansen,et al.  Impact of fin width on digital and analog performances of n-FinFETs , 2007 .

[6]  O. Faynot,et al.  Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit , 2012 .

[7]  Denis Flandre,et al.  Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits , 1996 .

[8]  C. Carabasse,et al.  Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors , 2010, 2010 International Electron Devices Meeting.

[9]  O. Faynot,et al.  Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances , 2013 .

[10]  Denis Flandre,et al.  Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures , 2007 .

[11]  V. Kilchytska,et al.  Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities , 2008, IEEE Transactions on Electron Devices.

[12]  V. Kilchytska,et al.  On the high-temperature subthreshold slope of thin-film SOI MOSFETs , 2002, IEEE Electron Device Letters.

[13]  O. Faynot,et al.  Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm , 2012, IEEE Electron Device Letters.

[14]  Marcelo Antonio Pavanello,et al.  Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation , 2007 .