Integration of SPAD in 28nm FDSOI CMOS technology

This paper reports the first experimental results obtained on a Single Photon Avalanche Diode (SPAD) implemented, in a 28nm FDSOI CMOS technology. The main originality relies on the integration of the SPAD below the buried oxide with the logic on-top in the thin silicon layer, providing an intrinsic 3D stack. The expected benefits are a much higher fill factor with embedded high performance and low power electronics. A test-chip has been fabricated with the commercial STMicroelectronics CMOS28FDSOI technology without any design rule violation nor process customization. SPAD breakdown has been investigated with electroluminescence cartography and breakdown voltage measurements. Afterwards, first dark count rate measurements are reported according to temperature and excess bias. To our knowledge, it is the first demonstration of SPAD devices in a FDSOI CMOS technology. Based on these encouraging results, the study will be pursued for more statistical data acquisition and for SPAD characterization under illumination.

[1]  A. Schenk.  Rigorous theory and simplified model of the band-to-band tunneling in silicon , 1993 .

[2]  G. Groos,et al.  Experimental extraction of the electron impact-ionization coefficient at large operating temperatures , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[3]  David Stoppa,et al.  Avalanche Photodiodes in Submicron CMOS Technologies for High-Sensitivity Imaging , 2011 .

[4]  L. Grant,et al.  A High-Performance Single-Photon Avalanche Diode in 130-nm CMOS Imaging Technology , 2012, IEEE Electron Device Letters.

[5]  Gerald S. Buller,et al.  Ge-on-Si Single-Photon Avalanche Diode Detectors: Design, Modeling, Fabrication, and Characterization at Wavelengths 1310 and 1550 nm , 2013, IEEE Transactions on Electron Devices.

[6]  E. Charbon,et al.  SPAD-based Sensors , 2013 .

[7]  E. Charbon.  Single-photon imaging in complementary metal oxide semiconductor processes , 2014, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.

[8]  S. Pellegrini,et al.  Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[9]  S. Pellegrini,et al.  Industrialised SPAD in 40 nm technology , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[10]  Edoardo Charbon,et al.  A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge , 2017, IEEE Electron Device Letters.

[11]  E. Charbon,et al.  A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[12]  A. Savoy-Navarro,et al.  Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology , 2017 .

[13]  Edoardo Charbon,et al.  A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppression , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).