Concurrent Error Detection in Multiply and Divide Arrays

A method proposed for concurrent error detection in ALU's is used in the design of multiplier and divider arrays. This method, called recomputing with shifted operands (RESO), can detect all errors caused by failures confined to a cell of the cellular array. The assumption that the failures are confined to a small area of an integrated circuit and the precise nature of the failures is not known is very applicable to VLSI circuits. RESO uses time redundancy for error detection and requires only a small increase in the hardware of a multiply and divide array.

[1]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[2]  J. Michael Yohe,et al.  Software for Interval Arithmetic: A Reasonably Portable Package , 1979, TOMS.

[3]  Janak H. Patel,et al.  Concurrent Error Detection in ALU's by Recomputing with Shifted Operands , 1982, IEEE Transactions on Computers.

[4]  John J. Shedletsky,et al.  Error Correction by Alternate-Data Retry , 1978, IEEE Transactions on Computers.

[5]  Frederick F. Sellers,et al.  Error detecting logic for digital computers , 1968 .

[6]  Thammavarapu R. N. Rao,et al.  Error coding for arithmetic processors , 1974 .

[7]  Algirdas Avizienis,et al.  Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design , 1971, IEEE Transactions on Computers.

[8]  H. Singh,et al.  A Generalized Pipeline Array , 1974, IEEE Transactions on Computers.

[9]  C. C. Beh,et al.  Do Stuck Fault Models Reflect Manufacturing Defects? , 1982, ITC.

[10]  John F. Wakerly,et al.  Error detecting codes, self-checking circuits and applications , 1978 .

[11]  Gernot Metze,et al.  Fault Detection Capabilities of Alternating Logic , 1978, IEEE Transactions on Computers.

[12]  Jacob A. Abraham,et al.  FAULT CHARACTERIZATION OF VLSI MOS CIRCUITS. , 1982 .

[13]  Gernot Metze,et al.  Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes , 1973, IEEE Transactions on Computers.

[14]  Oscar N. Garcia.  Error codes for arithmetic and logical operations , 1971 .

[15]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[16]  V. K. Agarwal,et al.  On-line Fault Detection And Correction In Microprocessor Systems , 1979 .

[17]  D. H. Jacobsohn,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..