Macromodeling of High-Speed Interconnects by Positive Interpolation of Vertical Segments

Abstract In this paper a novel macromodeling scheme is presented to model the per unit of length (p.u.l.) parameters of uniform transmission lines. In particular, it is focused on single on-chip interconnects, because their p.u.l. parameters are influenced by the presence of semiconductor (s) and as such exhibit a strong frequency-dependency, making the modeling process harder. Starting from a set of very accurate tabulated data samples, obtained by two-dimensional electromagnetic modeling, rational models for the four p.u.l. parameters are constructed. The novelty of the approach lies in the fact that the rational models are positive by construction and that a controllable accuracy is obtained. These models can then further be used to construct multivariate models, e.g., for variability analysis. Here, the novel scheme is applied to an on-chip inverted embedded microstrip line, of which the signal integrity behavior is assessed in both the frequency and the time domain, demonstrating the applicability of the macromodels.