Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor

As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and electronic design automation (EDA) industries, which may cause significantly increased mismatch between modeled and actual silicon behavior, and even IC failure in field. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch and perform in-field measurements. This paper presents a novel standard-cell-based sensor for reliability analysis of digital ICs (called Radic), in order to better understand the characteristics of gate, functional path aging and process variations' impact on timing performance, and perform in-field aging measurements. The Radic sensor has been fabricated on two floating gate Freescale SoCs in very advanced technology. The measurement results demonstrate that the resolution can be better than 0.1 ps, and the accuracy is kept throughout aging/process variation. Additionally, a built-in aging adaption system based on Radic sensor is proposed to perform in-field aging adaption. Simulation results verify that, comparing with designs with fixed aging guardband, the proposed aging adaption system releases 80% of aging timing margin, saves silicon area by 1.02%-3.16% at most targeting frequencies, and prevents aging induced failure.

[1]  John Keane,et al.  An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[3]  M.A. Alam,et al.  Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs , 2006, IEEE Transactions on Electron Devices.

[4]  Farinaz Koushanfar,et al.  N-variant IC design: Methodology and applications , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Wei Wang,et al.  On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[7]  David Blaauw,et al.  Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  K. Arabi,et al.  Dynamic digital integrated circuit testing using oscillation-test method , 1998 .

[9]  Magdy S. Abadir,et al.  Oscillation Ring Delay Test for High Performance Microprocessors , 2000, J. Electron. Test..

[10]  Enrico Macii,et al.  Temperature-Insensitive Dual- $V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Yun Zhang,et al.  Revisiting the Sequential Programming Model for Multi-Core , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[12]  Luca Benini,et al.  Aging-aware compiler-directed VLIW assignment for GPGPU architectures , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Xiaowei Li,et al.  ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation , 2011, IEEE Transactions on Computers.

[14]  Josep Torrellas,et al.  ReCycle:: pipeline adaptation to tolerate process variation , 2007, ISCA '07.

[15]  M. Omaña,et al.  Self-checking monitor for NBTI due degradation , 2010, 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW).

[16]  H. Reisinger,et al.  A Comparison of Very Fast to Very Slow Components in Degradation and Recovery Due to NBTI and Bulk Hole Trapping to Existing Physical Models , 2007, IEEE Transactions on Device and Materials Reliability.

[17]  Ming-Fu Li,et al.  Understand NBTI Mechanism by Developing Novel Measurement Techniques , 2008, IEEE Transactions on Device and Materials Reliability.

[18]  Luca Benini,et al.  Workload and user experience-aware Dynamic Reliability Management in multicore processors , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[19]  Mark Mohammad Tehranipoor,et al.  Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements , 2012, 2012 IEEE International Test Conference.

[20]  Shojiro Asai,et al.  New hot-carrier injection and device degradation in submicron MOSFETs , 1983 .

[21]  D. Varghese,et al.  A comprehensive model for PMOS NBTI degradation: Recent progress , 2007, Microelectron. Reliab..

[22]  David Blaauw,et al.  Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[23]  Saurabh Dighe,et al.  Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[24]  Luca Benini,et al.  Hierarchically Focused Guardbanding: An adaptive approach to mitigate PVT variations and aging , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Zhenyu Qi,et al.  Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay , 2009, 2009 10th International Symposium on Quality Electronic Design.

[26]  V. Reddy,et al.  A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[27]  Kaushik Roy,et al.  Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[28]  João Paulo Teixeira,et al.  Predictive error detection by on-line aging monitoring , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[29]  G. Groeseneken,et al.  Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs , 1988 .

[30]  U. Schwalke,et al.  Bias temperature reliability of n/sup +/ and p/sup +/ polysilicon gated NMOSFETs and PMOSFETs , 1993, 31st Annual Proceedings Reliability Physics 1993.

[31]  Shuguang Feng,et al.  Self-calibrating Online Wearout Detection , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[32]  M. Nunoshita,et al.  Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell , 1995, Proceedings of International Electron Devices Meeting.

[33]  David Blaauw,et al.  Dynamic NBTI management using a 45nm multi-degradation sensor , 2010, IEEE Custom Integrated Circuits Conference 2010.