Thermal analysis under different packaging processes for MEMS device with diaphragm

In this study, the induced stresses during packaging processes for MEMS device with diaphragm (membrane) were investigated by finite element analysis (FEA). Moving parts in MEMS device usually are the most important structures relevant to performance of sensing and actuating, therefore, the residual stress and distortion due to the heterogeneous structures with mismatch coefficient of thermal expansions (CTE) need to be avoided during packaging process. Two types packaging processes, die attach and flip-chip bond, were generally considered as most cost-effective way. Thus, in order to evaluate what is the better way for packaging MEMS device with thin membrane, we established four kinds of simulation models for comparison. In our models, the molding epoxy whether covered the MEMS chip or had a gap with MEMS chip was also considered for evaluation of the influence on thermal stresses in diaphragm structure during molding process. In addition, a sliding boundary condition instead of fixed-end boundary was set on the bottom surface of the package substrate for modeling the substrate handling on the heating stage by vacuum. From the simulation result, the resulting thermal stresses of the case as molding epoxy covered the MEMS chip are larger for either flip chip bonding or wire bonding, which means the molding method and material selection of epoxy are the key factors to reduce the thermal stress in diaphragm. Generally, flip chip bonding is the better packaging method for MEMS device because the influence of molding epoxy is less than wire bonding. This study introduced new concept of boundary condition for vacuum handling, and the simulation results can be employed to many MEMS applications such as silicon-based pressure sensor, capacitive MEMS microphone, etc.

[1]  O. Rusanen,et al.  Adhesives as a thermomechanical stress source-comparing silicones to epoxies , 1998, Proceedings of 3rd International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing 1998 (Cat. No.98EX180).

[2]  S. Hirsch,et al.  Test Chip for Characterization of Mechanical Stress Caused by Packaging Processes , 2006, 2006 1st Electronic Systemintegration Technology Conference.