A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms

Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in converting software implementation to register transfer level (RTL) hardware design. Such co-processor based systems show enhanced performance but often have greater power/energy consumption. Therefore, the automated synthesis of such accelerator IPs must be power-aware. Downstream power savings features such as clock-gating are unknown during HLS. Designer is forced to take such power-aware decisions only after logic synthesis stage, causing an increase in design time and effort. In this paper, we present a design automation solution to facilitate various granularities of clock-gating at high-level C description of the design.

[1]  Luca Benini,et al.  A scalable ODC-based algorithm for RTL insertion of gated clocks , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Ken-ichi Ishida,et al.  22.1 A 27MHz 11.1mW MPEG-4 Video Decoder LSI for Mobile Application , 2002 .

[3]  Niraj K. Jha,et al.  FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Magdy A. Bayoumi,et al.  Multiple voltage-based scheduling methodology for low power in the high level synthesis , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[5]  Sandeep K. Shukla,et al.  Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications , 2007, J. Low Power Electron..

[6]  Frank Emnett,et al.  Power Reduction Through RTL Clock Gating , 2001 .

[7]  Stefan Krugge,et al.  RTL Power Estimation , 2011 .

[8]  Sandeep K. Shukla,et al.  Power estimation methodology for a high-level synthesis framework , 2009, 2009 10th International Symposium on Quality Electronic Design.

[9]  James E. Stine,et al.  A framework for high-level synthesis of system on chip designs , 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

[10]  N. Agarwal,et al.  High-level FSMD design and automated clock gating with CoDeL , 2008, Canadian Journal of Electrical and Computer Engineering.