RISCE-a reduced instruction set circuit extractor for hierarchical VLSI layout verification based on interaction rules

The authors present a circuit extractor preserving the hierarchical layout structure isomorphically. As opposed to existing extractors, their approach permits all cell overlaps which are electrically meaningful. Mask operations based on stretched geometries handle topologically open and closed areas. A reduced set of model-independent instructions is introduced for device recognition. An existing implementation is discussed.<<ETX>>

[1]  S.N. Stevens,et al.  An integrated approach for hierarchical verification of VLSI mask artwork , 1985, IEEE Journal of Solid-State Circuits.

[2]  Louis Scheffer,et al.  Hierarchical Analysis of IC Artwork with User Defined Abstraction Rules , 1985, 22nd ACM/IEEE Design Automation Conference.

[3]  Kjell O. Jeppson,et al.  New algorithms for increased efficiency in hierarchical design rule checking , 1987, Integr..

[4]  Yiwan Wong.  Hierarchical Circuit Verification , 1985, 22nd ACM/IEEE Design Automation Conference.

[5]  Mark Horowitz,et al.  Resistance Extraction from Mask Layout Data , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Robert B. Tilove,et al.  Set Membership Classification: A Unified Approach to Geometric Intersection Problems , 1980, IEEE Transactions on Computers.

[7]  Y. Edmund Lien,et al.  Technology Tracking for VLSI Layout Design Tools , 1985, DAC 1985.

[8]  Gary M. Tarolli,et al.  Hierarchical Circuit Extraction with Detailed Parasitic Capacitance , 1983, 20th Design Automation Conference Proceedings.

[9]  Ahsan Bootehsaz,et al.  A Technology Independent Approach to Hierarchical IC Layout Extraction , 1986, 23rd ACM/IEEE Design Automation Conference.

[10]  Ulrich Golze,et al.  Ein hierarchischer inkrementeller Designrulechecker , 1986, it Inf. Technol..

[11]  Walter S. Scott,et al.  Magic's Circuit Extractor , 1985, IEEE Design & Test of Computers.

[12]  Christopher J. Van Wyk,et al.  Space Efficient Algorithms for VLSI Artwork Analysis , 1983, 20th Design Automation Conference Proceedings.

[13]  Todd J. Wagner.  Hierarchical Layout Verification , 1985, IEEE Design & Test of Computers.

[14]  A. Richard Newton,et al.  A Symbolic Design System for Integrated Circuits , 1982, 19th Design Automation Conference.