Controlled-load limited switch dynamic logic circuit

Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

[1]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[2]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[3]  J. Sivagnaname,et al.  Stand-by current in PD-SOI pseudo-nMOS circuits , 2003, 2003 IEEE International Conference on SOI.

[4]  Daniela De Venuto,et al.  International Symposium on Quality Electronic Design , 2005, Microelectron. J..

[5]  T.Y. Nguyen,et al.  Resonant clocking using distributed parasitic capacitance , 2004, IEEE Journal of Solid-State Circuits.

[6]  W. Belluomini,et al.  A double precision floating point multiply , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..