Analysis of via in multilayer printed circuit boards for high-speed digital systems

We have analyzed the effect of via in multilayer printed circuit boards (PCBs) on signal integrity and signal delay time of high-speed digital systems. First, the techniques of the circuit modeling of via are discussed. Electrical behaviors of via in interconnects according to its circuit model are characterized through HSPICE simulation. Based on these results, we show that via can behave as being capacitive or inductive according to the characteristic impedance of signal lines, which is different from the fact that via is generally regarded as being only capacitive. The proposed electrical characteristic of via is verified by results of TDR/TDT measurement of through-hole type via in 8-layer PCBs. Second, the methodology of measurement of delay caused by via is proposed. Because it is so difficult to measure the electrical delay of signal passing through one via, we extract the delay caused by single via from measuring the delay when the signal passes through several vias. For an example, we obtained the signal delay time of 12 psec caused by a throughhole type via in 8-layer PCBs. For just two vias, the delay time is about 24 psec and it is about 8% of flight time of 5 cm signal line.