Statistical Sampling Under Variability

In dealing with process parameter variations in nanometer-scale CMOS, modern CAD tools are moving towards a probabilistic view of circuit timing behavior instead of using worst-case corner models that lead to pessimism. The current approach in probabilistic timing analysis is to perform statistical static timing analysis by propagating standard distribution functions in the circuit (traditional SSTA). This approach cannot easily incorporate non-standard distributions and other issues in circuit arrival time. A fully mature traditional SSTA tool, capable of performing timing sign-off, is unlikely to be widely available soon. Our research on statistical sampling under variability captures the exact timing behavior of circuits under increasing process variation. The goal is to make Monte Carlo based SSTA a powerful alternative for timing analysis. We focus on developing techniques to generate samples in the process variation space with the aim of capturing maximum information about the circuit timing behavior with minimum samples. These samples can then be used for a Monte Carlo analysis to generate accurate timing models for the circuit. Recent results show that up to 44xfewer samples on the benchmark circuits studied are needed to arrive at comparable accuracy in timing estimation compared to a brute force random sampling approach. Our current direction is to extend the application of smart sampling techniques for statistical optimization and incremental timing analysis of digital circuits. This project is supported by the Semiconductor Research Corporation.