A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out

Energy minimization is a critical goal in size-constrained wireless sensors. Sensing elements are traditionally power hungry and require special attention in low energy systems. In this work, we study ultra-low power image sensors. In particular, we explore the use of aggressive voltage scaling in CMOS image sensors for applications ranging from retinal prostheses to battlefield monitoring and surveillance. We begin with a discussion of the challenges faced by a traditional 3T active pixel sensor as the supply voltage scales to 0.5 V and below. We then discuss an image sensor with pulse-width modulation read-out that is optimized for 0.5 V operation. A 0.13 ¿m test-chip with a 128 × 128 pixel array is shown to be functional with Vdd as low as 0.45 V with energy consumption of 140 nJ/frame at Vdd = 0.5 V (8.5 frames per second) and power consumption of only 700 nW at Vdd = 0.5 V (0.5 frames per second). A focus is also placed on quantifying the noise implications of low voltage operation on the test-chip, which has a measured signal-to-noise ratio of 23.4 dB in saturation at Vdd = 0.5 V.

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