Verification of systems containing counters

Systema containing counters have very large and deep state spaces, and the verification of properties on these systems can be very expensive in terms of memory space and computation time. We present a technique to automatically reduce the state space associated with the system on which some properties, that can ezpress both safeness and fairness constraints, have to be proved. In particular, we p.ve a set of conditions upon which some counters can be reduced to three state, non-deterministic machines, and the controllers can be simplified by removing the redundancy induced by their intemction with the counters, so that the verijication of tasks can be more easily performed.