Logic Suitability of 50-nm $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Beyond-CMOS Applications

We have experimentally studied the suitability of nanometer-scale In<sub>0.7</sub>Ga<sub>0.3</sub>As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm gate-length In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (Phi<sub>B</sub>) and insulator thickness (t<sub>ins</sub>) on the logic characteristics of In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs. The best 50-nm HEMTs with the highest Phi<sub>B</sub> and the smallest t<sub>ins</sub> exhibit an I<sub>ON</sub>/I<sub>OFF</sub> ratio in excess of 10<sup>4</sup> and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In<sub>0.7</sub>Ga<sub>0.3</sub>As HEMTs also show a logic gate delay (CV/I) of around 1 ps at a supply voltage of 0.5 V, while maintaining an I<sub>ON</sub>/I<sub>OFF</sub> ratio above 10<sup>4</sup>, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HEMTs hold a considerable promise.

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