0.5 kHz–32 MHz digital fractional-N frequency synthesizer with burst-frequency switch

A digital frequency synthesizer is proposed to support the burst-frequency switch for a motion controller. The proposed digital frequency synthesizer consists of a phase-locked loop (PLL) generating a 63-phase clock with a frequency of 128 MHz and a programmable open-loop fractional divider. It generates an output clock with a frequency resolution of 0.1% over a frequency range from 0.5 kHz to 32 MHz. The programmable open loop fractional divider generates an output clock such that its frequency is synthesized by periodically selecting the phase interpolated clock from the 63-phase clock of the PLL according to a digital control code. The frequency switching operation is performed within one cycle of the output clock owing to the operation of the phase selection of the open-loop fractional divider. The proposed digital frequency synthesizer is implemented using a 0.25 μm CMOS process with a 2.5 V supply. The measured rms time jitter of the output clock with 16 MHz frequency is approximately 8.06 ps.