A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of the transformation towards 4G. In this paper, we describe an energy efficient multi-Gbps LDPC decoder engine based on ASIP using Target tool suite. The ASIP core can be configured as half-layer paralleled or quarter-layer paralleled decoding, which offers a good trade-off between the throughput and power/area efficiency when compared to the state-of-art fully paralleled ASIC based multi-Gbps LDPC decoder. When the ASIP core is instantiated for 802.11ad, it achieved a throughput up to 5.3 Gbps at 5 iterations with a latency of less than 150 ns and a record energy efficiency of 4.3 pJ/bit/iteration in 40G TSMC technology for the coding rate 13/16, showing to be competitive versus published ASIC solutions.