Design of a path delay fault simulator for evaluation of abist generated stimuli

This paper describes the design of a fault simulator for delay faults in digital integrated circuits modeled by the path-delay fault model. The main purpose of the simulator is to evaluate test patterns from accumulator based generators. It may be used for any BIST-generated stimuli.

[1]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[2]  Spyros Tragoudas,et al.  On the nonenumerative path delay fault simulation problem , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Janusz Rajski,et al.  Arithmetic built-in self-test for DSP cores , 1999 .

[4]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[5]  Kwang-Ting Cheng,et al.  Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[6]  Spyros Tragoudas,et al.  Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations , 2007 .

[7]  Spyros Tragoudas,et al.  Color counting and its application to path delay fault coverage , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[8]  Spyros Tragoudas,et al.  Exact path delay fault coverage with fundamental ZBDD operations , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  B. Kapoor.  An efficient method for computing exact path delay fault coverage , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[10]  Vishwani D. Agrawal,et al.  An exact non-enumerative fault simulator for path-delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  Arnaud Virazel,et al.  Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences , 2001, J. Electron. Test..