Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices
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S. Ohnishi | N. Kawahara | Y. Kakuhara | N. Oda | H. Imura | K. Ueno | M. Tagami | H. Kunishima | S. Sone | K. Yamada | M. Sekine | Y. Hayashi
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