Factored multi-core architectures

Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alternative is to factor out or decouple large structures from critical pipeline loops. In this work, we combine prior techniques in factoring into a cohesive framework and extend this paradigm to more of the processor core. We propose an architecture where the large structures and latency tolerant performance accelerators are factored out of the processor core into helpers and the small and fast μ-core can be augmented with these latency tolerant helpers. This design will reduce the number of accesses to the large, power hungry structures and hence provide power savings with minimal impact on performance. Also this architecture allows the use of slower, more power efficient circuit designs for helpers. As the demands placed on the processor core varies between applications, and even between phases of an application, the benefit seen from any set of helpers will vary tremendously. If there is a single core, these auxiliary structures can be turned on and off dynamically to tune the energy/performance of the machine to the needs of the running application. This is achieved by taking advantage of the dynamic reconfigurability or polymorphism of helpers and allowing a core to adapt to changing applications, workloads, or phases. As more of the processor is broken down into helpers, and additional cores are added to a single chip, the μ-core design provides a unique opportunity of sharing helpers among the cores. This can be considered a middle point between two extremes of Simultaneous Multiprocessing (SMT) where most processor resources are shared among multiple threads running simultaneously and Chip Multiprocessing (CMP) where each thread is running on a separate core, possibly sharing only the second level on-chip cache. With the opportunity of sharing helpers among multiple cores, the decisions that are made about these structures become increasingly important. Which resources should be shared, how should they be allocated and how can we efficiently manage their power? To answer these questions at run-time, we need a set of shared helper management policies that can adaptively allocate resources in a way that takes into consideration the needs of each executing workload. In this work we describe the need for methods that effectively manage these helpers. Along with selectively enabling different helpers, our techniques determine whether to assign exclusive or shared ownership of helpers across multiple cores. By intelligently correlating run-time observations with past measured benefits, our management schemes enable dynamic selection of customized configurations which increase performance and reduce power consumption. Finally we evaluate the thermal efficiency of the μ-core architecture. We investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip. Specifically, the μ-core architecture presents an ideal platform for core swapping thanks to helpers that maintain the state of each process in a shared fabric surrounding the cores. This results in significantly reduced migration overhead, enabling seamless swapping of cores. Furthermore, we evaluate alternative approaches to spending the area overhead of the additional microcore, including larger μ-cores, CMP cores, and SMT cores running two-threaded workloads. We evaluate our design compared to different thermal management techniques such as global clock gating and frequency scaling.