High-performance low-power polyphase channelizer chip-set

A very-high-performance ultra-low-power signal processor chip-set has been developed for wideband adaptive radar and communications applications. The chip-set consists of a polyphase filter chip and a fast Fourier transform (FFT) chip. The chip-set performs polyphase channelization, which channelizes wideband digital data into multiple narrow subbands. The subsequent signal processing tasks such as adaptive beamforming, pulse compression, and space-time adaptive processing (STAP) are performed in the subband domain to mitigate dispersion effects. The power efficiency is achieved through highly optimized VLSI bit-level semi-systolic array technology. The chip-set was fabricated on a 0.25 micron bulk silicon CMOS process with the total two-chip die area of 1.6 square centimeters. The chip-set performs 54 billion arithmetic operations per second on 1.3 watts of power with 41 billion operations per second per watt power efficiency.

[1]  W.S. Song.  A new 3-GSPS 65-GOPS UHF digital radar receiver and its performance characteristics , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[2]  S. Biyiksiz,et al.  Multirate digital signal processing , 1985, Proceedings of the IEEE.

[3]  W.S. Song.  A two trillion operations per second miniaturized mixed signal radar receiver/processor , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).

[4]  W. S. Song.  VLSI bit-level systolic array for radar front-end signal processing , 1994, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers.

[5]  Che-Ho Wei,et al.  Efficient bit-level systolic array implementation of FIR and IIR digital filters , 1988, IEEE J. Sel. Areas Commun..