3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Three-dimensional (3D) circuit integration is a promising technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical planning of three-dimensional integrated circuits is substantially different from that of traditional planar integrated circuits, due to the presence of multiple layers of dies. To realize the full potential offered by three-dimensional integration, it is necessary to take physical information into consideration at higher-levels of the design abstraction for 3D ICs. This paper proposes an incremental system-level synthesis framework that tightly integrates behavioral synthesis of modules into the layer assignment and floorplan- ning stage of 3D IC design. Behavioral synthesis is implemented as a sub-routine to be called to adjust delay/power/variability/area of circuit modules during the physical planning process. Experimental results show that with the proposed synthesis-during-planning methodology, the overall timing yield is improved by 8%, and the chip peak temperature reduced by 6.6°C, compared to the conventional planning-after-synthesis approach.

[1]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[2]  Taewhan Kim,et al.  Timing variation-aware high-level synthesis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Xiaoxia Wu,et al.  Variability-driven module selection with joint design time optimization and post-silicon tuning , 2008, 2008 Asia and South Pacific Design Automation Conference.

[5]  Hai Zhou,et al.  Incremental exploration of the combined physical and behavioral design space , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[6]  Kiyoung Choi,et al.  Behavior-to-placed RTL synthesis with performance-driven placement , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[7]  Yuan Xie,et al.  Design space exploration for 3D architectures , 2006, JETC.

[8]  David Blaauw,et al.  Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.

[9]  Ranga Vemuri,et al.  Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[10]  Deming Chen,et al.  FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization , 2009, 2009 Asia and South Pacific Design Automation Conference.

[11]  Srinivas Katkoori,et al.  A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[12]  D. Helms,et al.  Binding, Allocation and Floorplanning in Low Power High-Level Synthesis , 2003, ICCAD 2003.

[13]  Yu Wang,et al.  Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[14]  Narayanan Vijaykrishnan,et al.  Interconnect and thermal-aware floorplanning for 3D microprocessors , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).