Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS

A synchronous DC-DC buck converter with integrated power switches is realized in a 65 nm CMOS technology, operating with a power inductor of 350 nH and an output capacitor of 470 nF as a chip-on-board prototype. The converter is designed for loads up to 120 mA and is targeted as replacement for LDOs in VLSI systems where multiple supplies must be provided. A dead time optimization algorithm continuously adjusts the dead times of the power switches in order to minimize body diode conduction losses. The whole converter occupies 0.088 mm2 chip area.