A 0.5-1V MTCMOS/SIMOX SRAM Macro with Multi-Vth Memory Cells

high-Vth one are also shown for comparison. The noise margins of both memory cells deceasc for reducing the supply voltage. But, the noise margin of the multi-Vth memory cell is more than twice that of the conventional one because the read-port of the multi-Vth cell does not affect the data-hold itode of the cell. The characteristics of the power dissipation of the multiplexer are shown in Fig. 5. The increase of'the Vth makes possible the reduction of the power dissipation of the multiplexer. When the threshold voltage is increased i'rom 0.15 to 0.35 V, the multiplexer can reduce the power dissipation by 60 % at 1 V and 80 % at 0.5 V. The delay-time characteristics of the multiplexer are shown in Fig. 6. The capacitance of the bit-line connected to the multi-Vth nlemory cell composed of SO1 devices with small junction capacitance is smaller than that of a memory cell composed of bulk devices. At 0.5 V, the delay time of the rnultiplexer of the SO1 SRAM with the bit-line capacitance of 0.4 pF, which comesponds to the sum of a row of 512 memory cells, is less than 75% that of the bulk SRAM with the bit-line capacitance of 0.8 pF. To verify the effectiveness of the multi-Vth memory cell scheme, we designed and fabricated a 64-Kb SRAM with 0.35-pm MTCMOS/SIMOX technology. The thicknesses of the gate-oxide, the active silicon layer, and the buriedoxide in the SIMOX-wafer are 7, 50, and 100 nm, respectively. The absolute values of the threshold voltage of lowand high-Vth MOSFETs are 0.15 and 0.35 V. A microphotograph of the SRAM is shown in Pig. 7 (a). The memory cell is 30% larger than the conventional single-port cell. The shmoo plots for evaluating the maxirnum operating frequency are shown in Fig. 7 (b). The maximum operating frequencies of over 100 and 20 MHz were confinned at the supply voltages of I and 0.5 V. The power consuniptions are 8 mW and 0.4 mW, respectively. The power consumption in the sleep mode is less than 0. I pW. The features of the SRAM are sunimarized in Table. Acknowledgment