Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

[1]  Takashi Maeda,et al.  Multi-stacked 1G cell/layer Pipe-shaped BiCS flash memory , 2009, 2009 Symposium on VLSI Circuits.

[2]  C. Chung,et al.  A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM) , 2012, 2012 International Electron Devices Meeting.

[3]  K. Tsunoda,et al.  Reduction in the reset current in a resistive random access memory consisting of NiOx brought about by reducing a parasitic capacitance , 2008 .

[4]  I. Baek,et al.  Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[5]  Yoon-Hee Choi,et al.  Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming , 2014, IEEE Journal of Solid-State Circuits.

[6]  Masahide Matsumoto,et al.  A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[7]  U-In Chung,et al.  Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[8]  H. Ahn,et al.  Realization of vertical resistive memory (VRRAM) using cost effective 3D process , 2011, 2011 International Electron Devices Meeting.

[9]  Kinam Kim,et al.  Technology challenges for deep-nano semiconductor , 2010, 2010 IEEE International Memory Workshop.

[10]  Franz Kreupl.  Access Device Options for New Memory Technologies , 2013 .

[11]  Duane Mills,et al.  19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[12]  U-In Chung,et al.  Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications , 2006, 2009 Symposium on VLSI Technology.

[13]  Dong Woo Kim,et al.  Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.

[14]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.