An efficient scaling procedure for Domino CMOS logic

The area required by Domino CMOS gates to support a specific response-time performance and capacitive load can be substantially reduced by scaling the NFET chain. A novel scaling procedure is described which requires far less CPU time than previous algorithms. The proposed scaling procedure has resulted in scaled Domino gates with channel area reductions similar to those given by the Monte Carlo/SPICE simulation. This procedure is applicable to other forms of dynamic logic.<<ETX>>

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