Innovating SRAM Design for Fast Process Related Defect Recognition and Failure Analysis

A special SRAM has been designed as a yield enhancement vehicle in a 0.35 f.DI'l CMOS technology. Extra design rules were added to encourage process defects on certain places and discourage them on others. From the failure signature of a memory cell (0 or 1 failure) and its failure extent (single cell, double cell, bitline, wordline, .. .) one can uniquely determine the process related cause of the failure. By this innovating design any process related defect can be linked with high probability to a certain failure signature and its extent which allows to fi nd easily the location of the failure. By simply testing the SRAM the main cause of failure can· be found which can help to drive yield improvement. In this paper the design philosophy of this SRAM is described, illustrated with some examples of process related defects that proved the usefulness and the strength of

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