A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation

In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (Sol) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, is proposed. Analytical models accounting for mobility degradation due to the vertical field, channel length modulation, drain induced barrier lowering and velocity saturation effects have been included in the model formulation. Also the action of parasitic bipolar transistor intrinsic to the SOI MOSFET has been considered. The proposed model considers the highly doped part of the GC transistor acting as a'main' transistor, whose drain voltage is modulated by the remaining part of the channel. Experimental results and two-dimensional simulated data were used to test the model, by comparing the drain current and some important characteristics for analog circuit design, such as the transconductance over the drain current ratio and output conductance, achieving a good agreement in both cases. (c) 2005 Elsevier Ltd. All rights reserved.

[1]  Juan Bautista Roldán,et al.  Study of the effects of a stepped doping profile in short-channel MOSFETs , 1997 .

[2]  Denis Flandre,et al.  Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs , 1994 .

[3]  Hong June Park,et al.  A charge sheet capacitance model of short channel MOSFETs for SPICE , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  D. Flandre,et al.  A physically-based continuous analytical graded-channel SOI nMOSFET model for analog applications , 2002, Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).

[5]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[6]  J. Fossum,et al.  A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD , 1988 .

[7]  Denis Flandre,et al.  A physically-based C/sub /spl infin//-continuous fully-depleted SOI MOSFET model for analog applications , 1996 .

[8]  C. T. Nguyen,et al.  Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's , 1994 .

[9]  Jerry G. Fossum,et al.  Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's , 1991 .

[10]  D. Flandre,et al.  Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors , 1991, IEEE Electron Device Letters.

[11]  Denis Flandre,et al.  Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects , 2000 .

[12]  Denis Flandre,et al.  High performance current mirrors using graded-channel SOI NMOSFETS , 2001 .

[13]  Denis Flandre,et al.  Analog circuit design using graded-channel silicon-on-insulator nMOSFETs , 2002 .

[14]  W. A. Lane,et al.  An enhanced SPICE MOSFET model suitable for analog applications , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Abhinav Kranti,et al.  Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .

[16]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[17]  Fabio Pellizzer,et al.  A new model of gate capacitance as a simple tool to extract MOS parameters , 2001 .

[18]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[19]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[20]  James B. Kuo,et al.  Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion , 2002 .

[21]  K. Yamaguchi,et al.  A mobility model for carriers in the MOS inversion layer , 1983, IEEE Transactions on Electron Devices.

[22]  K. N. Bhat,et al.  Numerical and charge sheet models for thin-film SOI MOSFETs , 1990 .

[23]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[24]  Denis Flandre,et al.  Analog performance and application of graded-channel fully depleted SOI MOSFETs , 2000 .

[25]  K. K. Young,et al.  Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs , 1988 .