Improved timing closure by analytical buffer and TSV planning in three-dimensional chips

In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planning in three-dimensional chips is presented in which the optimal location of both buffer and TSV of each net is determined simultaneously. In this method, twodimensional buffer planning formulation is extended to threedimensional era. Experimental results show that performance and probability of successful buffer/TSV insertion is increased considerably, especially for large and congested three-dimensional circuits.

[1]  Jason Cong,et al.  Buffer block planning for interconnect-driven floorplanning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[2]  Satoshi Goto,et al.  Buffer planning for 3D ICs , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[3]  Sheqin Dong,et al.  Simultaneous buffer and interlayer via planning for 3D floorplanning , 2009, 2009 10th International Symposium on Quality Electronic Design.

[4]  Taraneh Taghavi,et al.  Dragon2005: large-scale mixed-size placement tool , 2005, ISPD '05.

[5]  Hannu Tenhunen,et al.  Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs , 2007, ICCAD 2007.

[6]  Sachin S. Sapatnekar,et al.  A practical methodology for early buffer and wire resource allocation , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).