Vertical Double Gate MOSFET For Nanoscale Device With Fully Depleted Feature
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A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20–100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll‐off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.
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