Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI

This work presents a method for the design and characterization of a scalable ultra-wide voltage range static random access memory using an optimized 10 transistor bitcell, targeting minimum operating voltage, high yield and a Silicon-CAD correlation within 5%. The method is based on both static and dynamic metrics. The experimental validation was first performed in BULK CMOS 65 nm on a 32 kb memory array, then applied in 28 nm FDSOI on a 64 kb memory array. Over 10× energy reduction is achieved across a wide voltage range, i.e., from 1.2 V to 0.35 V while achieving high speed at the nominal voltage, i.e., 485 MHz in 65 nm BULK and 1 GHz in 28 nm FDSOI.

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